ARM has been quietly shifting way from mere gadgets and getting deeper into the network, and several announcements this week exemplify how far the company and its technology have come.
On Tuesday, Broadcom revealed plans to license the 64-bit ARMv8-A core for a new CPU with server class-performance based on Network Functions Virtualization (NFV). However, Broadcom's chips may not arrive till at least mid-2014 as they are planned for production on a 16-nanometer process node.
Further, the semiconductor company is partnering with ARM to create an open, ISA-independent, standards-based NFV software environment for the ARM ecosystem with virtualized accelerators for networking, communications, big data, storage and security applications. The companies said they are working with leading service providers, the Linaro Networking Group and European Telecommunications Standards Institute (ETSI) to standardize the environment's programming model, tool chains, application programming interfaces and networking-specific libraries across the industry.
Broadcom previously relied upon the MIPS architecture but has been gradually adding ARM's architecture to its lineup. This most recent announcement puts ARM into all of Broadcom's major product units and is a reflection of ARM's new 64-bit architecture, which can handle large, complex computing, according to SDNCentral.
In related news, CEVA rolled out the CEVA-XC4500 DSP, which it says is the first vector floating-point DSP specifically designed for advanced wireless infrastructure solutions that require higher performance processing solutions. The DSP is available for licensing and is already in design with a top wireless network gear vendor, said the company.
According to Eran Briman, vice president of marketing at CEVA, "We collaborated closely with ARM to ensure comprehensive support for their latest industry-standard interconnect and coherency protocols, enabling our mutual customers [to] leverage the inherent advantages of designing ARM + CEVA-XC multi-core SoCs."
Ceva said its new DSP is aimed at providing performance and power efficiency for software-defined wireless infrastructure applications and is targeted at macrocells, small cells, cloud-RAN, digital front-end and backhaul.
Meanwhile, Freescale Semiconductor announced its QorIQ LS1 family of communications processors based on the core-agnostic, software-aware Layerscape system architecture. The devices are engineered to support a broad range of power-sensitive networking applications, as well as additional fast-growing product categories including Internet of Things gateways and industrial automation and control equipment.
Each of the three QorIQ LS1 family processors features two ARM Cortex-A7 cores, which are typically used in battery-powered applications such as smartphones and have been enhanced with error detection and correction technology.
"Freescale's QorIQ LS1 series is an impressive example of how application-specific IP and SoC design can combine with ARM technology to create a flexible and integrated product," said Charlene Marini, vice president, marketing, embedded segments, ARM. Marini added that Freescale's adoption of ARM Cortex-A7 processors "underscores the exciting role that ARM is playing in bringing advanced energy efficiency and intelligence to the world's data networks."
Freescale's QorIQ communications processor product line includes ARM-based devices as well as PowerPC-based devices. According to a Freescale spokesman, this is "a benefit of the 'core agnostic' nature of our QorIQ Layerscape architecture."
- see this Broadcom release
- see CEVA release
- see this Freescale release
- see this SDNCentral article
- see this ZDNet article
- see this GigaOM article
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ZTE licenses CEVA digital signal processor for TDD/FDD LTE infrastructure
Broadcom targets 10 Gbps Ethernet backhaul for LTE
Freescale adds metrocell SoC for LTE, HSPA+
Freescale touts single-architecture SoCs for macro and small cells
Story updated Oct. 17, 2013, to add additional clarifying information from Freescale.